Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Coefficient, Pass and Code-Block Parallel Architecture for FBP Coding in JPEG2000

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Xin Fan ; Peking Univ., Beijing ; Chao Xu

This paper presents a novel hardware architecture for fractional bit-plane coding in JPEG2000. The computation of coefficient's significance state is prioritized from the coding pass, and a concise circuit is proposed to predict the significant state. By exploiting the information, moreover, we present the triple parallel architecture to speed-up fractional bit-plane coding: (1) coefficients in a stripe-column are coded in parallel; (2) three coding passes are performed concurrently; (3) two code-blocks are cross-encoded. Experiental results in FPGA platform show that, by sharing all the control logics efficiently, the triple parallel architecture can encode at a speed 12 times as fast as that of the primary serial-coding mode, while occupies less than 4 times logic cells and double internal memories.

Published in:

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Date of Conference:

10-13 Dec. 2006