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This paper presents a novel hardware architecture for fractional bit-plane coding in JPEG2000. The computation of coefficient's significance state is prioritized from the coding pass, and a concise circuit is proposed to predict the significant state. By exploiting the information, moreover, we present the triple parallel architecture to speed-up fractional bit-plane coding: (1) coefficients in a stripe-column are coded in parallel; (2) three coding passes are performed concurrently; (3) two code-blocks are cross-encoded. Experiental results in FPGA platform show that, by sharing all the control logics efficiently, the triple parallel architecture can encode at a speed 12 times as fast as that of the primary serial-coding mode, while occupies less than 4 times logic cells and double internal memories.
Date of Conference: 10-13 Dec. 2006