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An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology

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3 Author(s)
Arbat, A. ; Univ. de Barcelona, Barcelona ; Dieguez, A. ; Samitier, J.

A low power successive approximation analog-to-digital converter is presented operating at 1.2 V supply. The circuit has been designed in a 0.13 μm standard CMOS technology. The power consumption while converting is 13 μW, and in standby mode the power is reduced to 5.8 μW. The resolution is programmable between 1 to 8 bits. It can work from 500 Hz up to 50 kHz clock frequencies.

Published in:

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Date of Conference:

10-13 Dec. 2006