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This paper presents a methodology for the design of a CMOS low-noise amplifier (LNA) operating at 5.5GHz. As an example, the design of a narrow-band cascode LNA intended for WiMax application in the frequency range from 5-6GHz is analyzed, using an 120nm CMOS technology. Trade-offs in the design, such as noise figure, gain, linearity are explored, based on the inversion coefficient and channel length of the MOS transistors. The design accounts for the effect of induced gate noise in the MOSFETs using the EKV3 model and accounts for non-ideal inductors. It is clearly shown how reduced channel length also leads to lower levels of inversion for best LNA performance.