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A Self-Tuning Configurable Cache

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2 Author(s)
Gordon-Ross, A. ; Univ. of California, Riverside ; Vahid, F.

The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can reduce memory subsystem energy by 62% on average. We introduce a self-tuning cache that performs transparent runtime cache tuning, thus relieving the application designer and/or compiler from predetermining an application's cache configuration. The self-tuning cache applies tuning at a determined tuning interval. A good interval balances tuning process energy overhead against the energy overhead of running in a sub-optimal cache configuration, which we show wastes much energy. We present a self-tuning cache that dynamically varies the tuning interval, resulting in average energy reduction of as much as 29%, falling within 13% of an oracle-based optimal method.

Published in:

Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE

Date of Conference:

4-8 June 2007