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Jitter Characteristic in Charge Recovery Resonant Clock Distribution

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3 Author(s)
Mesgarzadeh, B. ; Linkoping Univ., Linkoping ; Hansson, M. ; Alvandpour, A.

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 7 )