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A Low-Power Embedded SRAM for Wireless Applications

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3 Author(s)
Cosemans, S. ; Katholieke Univ, Leuven ; Dehaene, W. ; Catthoor, F.

This paper introduces a novel ultra-low-power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off between area, delay and active and passive energy consumption for low-power embedded SRAMs. The design targets wireless applications that require a moderate performance at an ultra-low-power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low-swing write technique and a distributed decoder. An 8-KB 5T SRAM was fabricated in a 0.18-mum technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32-KB SRAM.

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Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 7 )