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Moving Carefully Towards Model-based Layout Optimization and Checking

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2 Author(s)
Hibbeler, J.D. ; IBM, Essex Junction ; Maynard, D.N.

IBM has taken several steps in developing an analysis and optimization framework for VLSI layouts. We have deployed automated tools to reduce the sensitivity of designs to certain defect mechanisms in the manufacturing process. We see a clear need for expanding and refining tMs work and then integrating it with rigorous characterization of manufacturing processes and at the same time developing and integrating an overall trade-off theory showing the interaction of different layout-based yield-enhancement actions.

Published in:

Advanced Semiconductor Manufacturing Conference, 2007. ASMC 2007. IEEE/SEMI

Date of Conference:

11-12 June 2007

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