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Novel CMOS latch with clock hysteresis

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1 Author(s)
D. W. R. Orton ; Racal Research Limited, Reading, UK

A latch circuit is described which tolerates the use of slow and skewed clock signals. The low-complexity circuit has been shown to provide a safe alternative to the use of non-overlapping clocks, and enables the minimisation of clock interconnection and power.

Published in:

Electronics Letters  (Volume:23 ,  Issue: 23 )