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3 μm VLSI processing element using the CORDIC algorithm

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2 Author(s)
G. J. Vaudin ; University of Warwick, VLSI Architectures Group Department of Computer Science, Coventry, UK ; G. R. Nudd

A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor has been designed in 3 μm CMOS technology such that when organised in a pipeline array it can achieve computation rates equivalent to 50 ns, suitable for most real-time signal and image processing applications.

Published in:

Electronics Letters  (Volume:23 ,  Issue: 21 )