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Reconvergent fanout analysis and fault simulation complexity of combinational circuits

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2 Author(s)
Maamari, F. ; McGill University, VLSI Design Laboratory, Department of Electrical Engineering, Montreal, Canada ; Rajski, J.

The detectability of reconvergent fanout stem faults in a combinational logic circuit can be determined by explicitly simulating the faults within limited regions of the circuit. These regions are defined, and an estimate of the fault simulation complexity of the circuit is obtained. Results are presented for ten benchmark circuits.

Published in:

Electronics Letters  (Volume:23 ,  Issue: 21 )

Date of Publication:

October 8 1987

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