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Electrostatic discharge testing of integrated circuits using step-stress transients or multiple transients

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2 Author(s)
R. N. Shaw ; British Telecom Research Laboratories, Ipswich, UK ; R. D. Enoch

A model has been developed which accounts for the damage behaviour of the on-chip input protection diode of an IC subjected either to multiple-transient testing or to step-stress testing.

Published in:

Electronics Letters  (Volume:22 ,  Issue: 15 )