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High-speed ring oscillators using planar p+-gate n-AlGaAs/GaAs 2DEG FETs

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4 Author(s)
Suzuki, Y. ; NEC Corporation, Microelectronics Research Laboratories, Kawasaki, Japan ; Hida, H. ; Toyoshima, H. ; Ohata, K.

An E/R DCFL ring oscillator has been fabricated using a planar n-AlGaAs/GaAs 2DEG enhancement FET with p+-gate structure. For 1 ¿m gate length E-FETs, the standard deviation of threshold voltage was as small as 17.6 mV at 0.016 V average threshold voltage. At room temperature, a gate propagation delay of 15 ps/gate at a 5.25 mW/gate power dissipation was obtained from a 25-stage ring oscillator. A small minimum power-delay product of 14 fJ/gate was attained at 0.65 V supply voltage.

Published in:

Electronics Letters  (Volume:22 ,  Issue: 12 )