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Overlaid CMOS

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4 Author(s)
Malhi, S.D.S. ; Texas Instruments Incorporated, Semiconductor Process & Design Center, Dallas, USA ; Bean, K.E. ; Sunderesan, R. ; Hite, L.R.

A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.

Published in:

Electronics Letters  (Volume:22 ,  Issue: 11 )