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Performance analysis of interconnection networks of a modified model for synchronous multiprocessors

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2 Author(s)
A. Pombortsis ; University of Thessaloniki, Digital Systems & Computers Laboratory, Department of Physics & Mathematics, Thessaloniki, Greece ; C. Halatsis

The letter presents an analysis of a modified model for synchronous multiprocessor systems. In this model, besides the shared memory modules, each processor has a private memory. The memory references of each processor are not uniformly distributed among the memory modules. The interconnection network is considered to be either a crossbar or a shared bus.

Published in:

Electronics Letters  (Volume:22 ,  Issue: 4 )