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Topology dependence of floating gate faults in MOS integrated circuits

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2 Author(s)
Renovell, M. ; Université des Sciences et Techniques du Languedoc, Laboratoire d'Automatique et de Microélectronique de Montpellier, Laboratoire associé au CNRS (UA 371), Montpellier, France ; Cambon, G.

Models for floating gate faults in MOS integrated circuits are introduced. It is experimentally demonstrated that these models are mask-topology-dependent. The logic state of the gate can be stuck-at, undefined or influenced. In the case of an influenced gate a `pseudo-MOS transistor¿ is defined.

Published in:

Electronics Letters  (Volume:22 ,  Issue: 3 )