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Design of a 1-Volt and μ-power SARADC for Sensor Network Application

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3 Author(s)
Sang-Hyun Cho ; Dept. of Inf. & Commun., Gwangju Inst. of Sci. & Technol. ; Chang-Kyo Lee ; Jong-In Song

Design and verification of a low-voltage, low-power, and extremely small area successive approximation registered analog-to-digital converter (SARADC) for sensor network applications are presented. The 8-bit SARADC employed a capacitor-based hybrid digital-to-analog converter and a simplified digital control block to achieve low power consumption and small area and a charge pumped switch to reduce non-linearity errors originating from operation of the switch in low-voltage and low-power condition. The 8-bit SARADC, implemented by the 0.18μm TSMC SOI CMOS process, has the power consumption of 1.8μW at the power supply voltage of 1.0V and the sampling rate of 10k sampling per second, which is one of the lowest power consumption for ADCs ever presented.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007