Power Consumption Analysis of Flip-flop Based Interconnect Pipelining

This paper presents an in-depth analysis of power consumption in flip-flop based wire pipelining. A comparison for the power consumed by the repeaters and the inserted flip-flops are given for different technology nodes, and it has been observed that the power consumed by the repeaters is much higher than the power consumed by the flip-flops. A relationship between the number of inserted flip-flops and repeater size with the power consumption is demonstrated in this paper. Here it has also been illustrated that there is a lower bound for the power consumed by a certain interconnect pipelining scheme, since number of flip-flops and repeater sizes can not lowered beyond certain limit due to the solidity requirement, which is determined by maximum allowable bit error rate.