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In this paper, we propose an automatic test pattern generation (ATPG) scheme for low power launch-off-capture (LOC) transition test. Two techniques are explored in the proposed ATPG. A bidirectional X-filling, in which both line justification and logic simulation are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. For vectors producing very large capture power, a test vector replacement scheme is applied to efficiently reduce the peak capture power. The proposed method does not change the test architecture, and thus no hardware overhead is required. Experimental results show that the proposed scheme outperforms previous method by 50% in both peak power and average capture power.