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Low-power design technique for flash A/D converters based on reduction of the number of comparators

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3 Author(s)
Sato, T. ; Graduate Sch. of Sci. & Eng., Tokyo Inst. of Technol. ; Takagi, S. ; Fujii, M.

This paper proposes a low-power, small chip area design technique for flash analog-to-digital converters (A/D converters). The proposed technique reduces power consumption of flash A/D converters by 50 % reduction of the number of comparators. Because output signals of flash A/D converters are thermometer code, only a few comparators whose reference voltages are around the input signal are significant and the other comparators can be removed. A novel track and hold circuit (T/H circuit) which can exchange its two balanced output signals is introduced. Thanks to the T/H circuit, the required input range of the comparator is limited to half of that of conventional one. The proposed A/D converter using the proposed T/H circuit can realize the same accuracy with the conventional one. The proposed technique is applied to a 6-bit 528 Msamples/s A/D converter realization. Its power consumption is evaluated by HSPICE simulations. It is confirmed that the proposed technique can save 34% of power consumption compared with conventional one.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007