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Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture

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4 Author(s)
Yamaguchi, K. ; Graduate Sch. of Inf. Sci. & Technol., Tokyo Univ. ; Watanabe, Y. ; Komuro, T. ; Ishikawa, M.

Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to handle highly complicated recognition tasks. We describe a multi-SIMD architecture and the design of a vision processor based on it for carrying out such difficult image recognition tasks. The proposed architecture consists of two SIMD parallel processing modules and a shared memory, allowing highly parallelized and flexible computation of complicated recognition tasks, which were difficult to process on a conventional massively parallel SIMD architecture. We designed a prototype vision processor for evaluation purposes and confirmed that the processor could be implemented in FPGA.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007