By Topic

A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Soon-Ik Cho ; Dept. of Electron. & Comput. Eng., Korea Univ., Seoul ; Suki Kim ; Shin-Il Lim ; Kwang-Hyun Baek

The authors propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18mum 1-poly 4-metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, the authors employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz input while consuming 296mW and 5.86bit at 1240MHz input while consuming 341mW operating at 2.5GS/s clock frequency. This corresponds to figure-of-merit numbers (FoM) of 2.36 pJ/convstep at 1240MHz input. The total active area is 0.71mm2.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007