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The authors propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18mum 1-poly 4-metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, the authors employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz input while consuming 296mW and 5.86bit at 1240MHz input while consuming 341mW operating at 2.5GS/s clock frequency. This corresponds to figure-of-merit numbers (FoM) of 2.36 pJ/convstep at 1240MHz input. The total active area is 0.71mm2.