Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes

This paper describes the design of an ultra low power CMOS PLL clock synthesizer targeting wireless sensor applications that require low minimum power dissipation. Based on integer-N architecture, the PLL clock synthesizer produces a 100 kHz output signal from a reference input signal generated using an on-chip crystal oscillator operating at 32.768 kHz. Fabricated in a 0.6-mum N-well CMOS process technology, the PLL achieves a power consumption of 20 muW with a frequency accuracy of plusmn13 Hz.