By Topic

A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Baoyong Chi ; Institute of Microelectronics, Tsinghua University, Beijing 100084, China ; Xueyi Yu ; Woogeun Rhee ; Zhihua Wang

In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a DeltaSigma modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) DeltaSigma fractional-N PLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007