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A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-μm CMOS

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4 Author(s)
Abdelrahim, T.A. ; Dept. of Electr. Eng., Ain Shams Univ., Cairo ; Elesseily, T. ; Ahmed Saad Abdou ; Sharaf, K.M.W.

This paper presents the design of a dual-band L1/L2 global positioning system (GPS) receiver. A low-IF architecture was used for dual-band operation with analog on-chip image rejection. The receiver is composed of dual-band LNAs and down-conversion mixers, a complex variable-gain channel select filter, analog AGC loop, and a 2-bit analog-to-digital converter. The receiver is to be integrated with a phase-locked-loop synthesizer designed in another work (Elesseily and Sharaf, 2006), The digital tracking correlator of the receiver is designed and implemented on FPGA. The acquistion part of the digital receiver is still under development using embedded software. The digital correlator showed successful operation with a signal of -30dB SNR at the A/D output. Designed in a 0.13 μm CMOS technology, the receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4.3 dB and 3.6 dB, and input compression points of -75 dBm and -78 dBm for L1 and L2 bands, respectively. The complex variable-gain channel select filter provides image rejection better than 25 dB and gain control range over 60 dB. The receiver consumes 12 mW from a 1.2-V supply.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007