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This paper presents the design of a Viterbi decoder for the multiband OFDM (MB-OFDM) ultra-wideband (UWB) communication systems. To achieve the highest data rate desired with hardware efficiency, a folded sliding block architecture is utilized. For lower data rates, some of the processing elements (PE) in the Viterbi decoder are disabled to save power. The design has been implemented on FPGA and the throughput can be up to 432 Mbps on a Xilinx Virtex-4 device.