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VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

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3 Author(s)
Yang Sun ; Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX ; Karkooti, M. ; Cavallaro, J.R.

A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multi-rate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between frac14 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007

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