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Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

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2 Author(s)
Stephane Badel ; Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. Email: ; Yusuf Leblebici

In this paper, the authors study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages. The authors show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. The authors propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25mum, 0.18mum and 0.13mum CMOS).

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007