A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. But if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a register relocation method that reduces the number of registers while keeping the target clock period. The proposed method reduces the number of registers in the practical time in experiments.