Cart (Loading....) | Create Account
Close category search window

A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 μm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Cheng Chen ; Dept. of Electroscience, Lund Univ. ; Jiren Yuan

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (≫250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Spectre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.