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Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

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4 Author(s)
Kiran Gunnam ; Department of Electrical and Computer Engineering, Texas A&M University, TX 77840. Email: kirang@ece.tamu.edu ; Gwan Choi ; Weihuang Wang ; Mark Yeary

We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2times.

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007