A New Statistical Approach for Glitch Estimation in Combinational Circuits

Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techniques. Glitches are not functionally significant in synchronous designs, but they consume a lot of power. By reducing glitching activity, we can reduce the dominant term in the power consumption of CMOS digital circuits. In this paper, we present a new method to estimate the glitching activity for different circuit nodes. The method is robust and produces accurate glitch probability numbers early in the design cycle. It does not have much overhead and it alleviates existing compute-intensive algorithms/methods.