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A New Frame Recompression Algorithm Integrated with H.264 Video Compression

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3 Author(s)
Yongje Lee ; System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd, Gyeonggi-Do, Korea. ; Chae-Eun Rhee ; Hyuk-Jae Lee

To reduce the size and bandwidth requirement of a frame memory for video compression, a number of memory recompression algorithms have been proposed. These previous algorithms are performed independently of a video compression standard and therefore do not take advantage of the information obtained during the processing of the compression standard. This paper proposes a new recompression algorithm that makes use of the information from H.264 intra prediction results. The proposed algorithm decomposes a frame into 4times4 blocks which are then compressed into 64-bit segments. The result of 4times4 intra prediction is used to select the scan order of the 4times4 block and DPCM (differential pulse code modulation) is performed along this scan order. Then, the DPCM results are further compressed by Golomb-Rice coding. The proposed recompression algorithm is implemented in hardware and integrated with an H.264 encoder. The proposed algorithm improves the average PSNR by 2.9dB compared to the previous work in (Lee, 2003). The hardware cost for the implementation of the recompression algorithm is 28 K gates and the additional latency to read the compressed frame memory is 162 cycles per a macroblock

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007