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"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC

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3 Author(s)
McNeill, J.A. ; Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA ; Goluguri, S. ; Nair, A.

The "split ADC" architecture concept is applied to correction of errors due to nonlinearity of an open-loop residue amplifier in a pipeline ADC. Determination of calibration parameters and correction of errors takes place entirely in the background in the digital domain; no interaction with analog circuitry is required. An algorithm exhibiting convergence of calibration parameters in fewer than 100 000 conversions is presented.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007

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