By Topic

Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Itradat, A. ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que. ; Ahmad, M.O. ; Shatnawi, A.

A great deal of research has been conducted in the area of scheduling DSP data flow graphs (DFG) onto multiprocessor systems. This paper introduces a new scheduling and allocation algorithm for the synthesis of DSP applications. The proposed technique provides the designer with a greater flexibility to explore the design space using a hybrid arithmetic functional unit library composed of both fixed operation-specific units and reconfigurable functional units capable of executing multiple operations. A novel reconfigurable multiplier called morphable multiplier is incorporated in the proposed synthesis technique. We show that moving from a fully homogenous multiprocessor design using fixed multiple-operation units (i.e., ALUs) to a fully heterogeneous design using fixed operation-specific units (i.e., adders or multipliers) results in decreasing the area of the design, but increasing the inter-processor communication overhead. However, a hybrid multiprocessor architecture that uses a hybrid arithmetic functional unit library composed of both fixed operation-specific units and run-time reconfigurable multiple-operation units brings about a trade-off between the area and the inter-processor communication overhead

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007