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A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoC

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2 Author(s)
Hirokazu Tohya ; ICAST, Inc., 4-9-1-202, Myojincho, Hachioji, Tokyo 192-0046, Japan. E-mail: h-toya@icastech.jp ; Noritaka Toya

The novel design methodology of the on-chip power distribution network (PDN) is presented in this paper. The low-impedance lossy line (LILL) technology is used for the on-chip PDN instead of the on-chip capacitors. The on-chip PDN improves the performance of the SoC and suppresses the electromagnetic interference (EMI) of the SoC. The solitary electromagnetic wave (SEMW) concept is proposed. The SEMW is generated by the on-chip inverter, and its waveform is similar to a half-wave of a sinusoidal. An analysis of the effect of the SEMW concept, SPICE simulation result, and an example of the on-chip LILL structure, and the parallel-plate ceramic (PPC) LILL for on-board PDN are presented.

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007