Referenced Items are not available for this document.
In this paper, an embedded jitter measurement system is presented. The system uses the Vernier delay method to achieve high resolution. The jitter test circuit is implemented using current-mode logic, so it is fast enough for testing today's high-speed I/O signals such as PCI Express. And the differential structure also makes the circuit immune to common-mode noise. Other advanced jitter measurement functions can be added to the time interval analyzer, (TIA) system presented here. Simulation results show that the TIA system can be used with low-cost ATEs to meet jitter measurement requirements
Published in:
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Date of Conference: 27-30 May 2007
- Page(s):
- 153 - 156
- E-ISBN :
- 1-4244-0921-7
- Print ISBN:
- 1-4244-0920-9
- INSPEC Accession Number:
- 9508214
- Conference Location :
- New Orleans, LA
- Digital Object Identifier :
- 10.1109/ISCAS.2007.378244
- Product Type:
- Conference Publications
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