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A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

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5 Author(s)
Tortosa, R. ; Inst. de Microelectron. de Sevilla, IMSE-CNM, Sevilla ; Aceituno, A. ; de la Rosa, J.M. ; Rodriguez-Vazquez, A.
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This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade SigmaDeltamodulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007