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Tutorial 12: Challenges and Opportunities of Digital Design in Nanoscale CMOS

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1 Author(s)
Chuang, Ching-Te Kent ; IBM, New York, USA

This tutorial reviews the challenges and opportunities of high-performance digital design in nanoscale CMOS technologies. The device structure evolution, material enhancement, and major design challenges are discussed. Examples of logic circuit and SRAM design techniques to overcome the challenges and to mitigate various performance/reliability constraints in conventional planar CMOS technology are given. Scaled/emerging technologies such as scaled PD/SOI, UT/SOI, strained-Si channel device, hybrid orientation technology, and multi-gate FinFET are addressed with particular emphases on the implications and impacts on circuit design. Finally, novel logic circuit, SRAM, and power-gating schemes exploiting unique structures and properties of emerging devices are discussed.

Published in:

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Date of Conference:

27-30 May 2007