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High-Q Slow-Wave Transmission Line for Chip Area Reduction on Advanced CMOS Processes

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2 Author(s)
Lai, I.C.H. ; Tokyo Univ., Chiba ; Fujishima, M.

A slow-wave transmission line (SWTL) structure has been presented in earlier works for advanced CMOS processes. This structure has a high quality factor and low attenuation. It is now shown that this structure also allows slow-waves to propagate which results in a short wavelength for chip area-reduction. It is shown in this work, using test structures measurements, that the wavelength-reduction property can be varied by the coplanar dimensions of the lines. This structure is also designed to satisfy the stringent density requirements of advanced CMOS processes. Test structures were fabricated using CMOS 90 nm process technology with measurements made up to 110 GHz.

Published in:

Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on

Date of Conference:

19-22 March 2007