Demonstration of Metal-Gated Low V_t n-MOSFETs Using a Poly-Si/TaN/Dy₂O₃/SiON Gate Stack With a Scaled EOT Value

In this letter, we report that by using a thin dysprosium oxide (Dy₂O₃)cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (V_t) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy₂O₃ cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.