By Topic

A Novel Dual-Doping Floating-Gate (DDFG) Flash Memory Featuring Low Power and High Reliability Application

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)

In this letter, a novel Flash memory cell structure using dual doping polysilicon (p-n-p) as the floating gate, which can improve the cell performance and reliability, is proposed. Except for an additional large-angle tilted implantation, the fabrication technology is essentially compatible with standard CMOS technology. Measured results show that the new Flash cell with p-n-p-type floating gate can achieve higher programming speed, lower power, comparable erasing performance, and better data retention characteristics in comparison with conventional n-type floating-gate structure.

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 7 )