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Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology

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7 Author(s)
Daeik Kim ; IBM Semicond. Res. and Dev. Center, Hopewell Junction ; Jonghae Kim ; Jean-Olivier Plouchart ; Choongyeun Cho
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This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configuration's pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.

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IEEE Electron Device Letters  (Volume:28 ,  Issue: 7 )