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A Low-Power Multiplier With the Spurious Power Suppression Technique

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2 Author(s)
Kuan-Hung Chen ; Feng-Chia Univ., Tai-Chung ; Yuan-Sun Chu

This paper provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e., using registers and using and gates, to assert the data signals of multipliers after the data transition. The SPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. Adopting a 0.18-mum CMOS technology, the proposed SPST-equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:15 ,  Issue: 7 )

Date of Publication:

July 2007

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