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n+ self-aligned-gate AlGaAs/GaAs heterostructure FET

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5 Author(s)
Mizutani, T. ; NTT Atsugi Electrical Communication Laboratories, Atsugi, Japan ; Arai, K. ; Oe, K. ; Fujita, S.
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The n+ self-aligned-gate technology for high-performance AlGaAs/GaAs heterostructure FETs employing rapid lamp annealing have been studied. The large transconductance of 330 mS/mm at 300 K and 530 mS/mm at 83 K was obtained for the 0.7 ¿m gate length device, by reducing the source resistance to 0.6 ¿mm. The minimum delay time of 18.7 ps was obtained with a power dissipation of 9.1 mW at 300 K. The standard deviation of the delay time was as small as 1.1 ps at a fixed bias of 2.5 V.

Published in:

Electronics Letters  (Volume:21 ,  Issue: 15 )

Date of Publication:

July 18 1985

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