By Topic

High-speed GDDRIII System Implementation by Channel Signal and Power Integrity Factorial Design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jimmy Hsu ; VIA Technologies, Inc., Taipei, 1F, 531, Chung-Cheng Rd., Hsin-Tien, Taipei, Taiwan. Jimmy, 886-2-22185452 ext. 6643 ; Randy Hsiao

Implementing single-ended Graphic Double Data Rate III (GDDRIII) interface at 1.6 Gbps in production is challenging in the current graphic memory environment. This paper proposes a system design method in the signal and power integrity perspective which could perform the channel factorial electrical analyses to figure out the parameter influence. This methodology could be usefully applied in the budget control and the electrical physical constraint setup on the design phase, and critical parameters could be list down and optimized in the pre-design analysis. We can make a proper compromise among the different design electrical parameters with the corresponding penalties to robustly function up to 1.6 Gbps in the graphic controller data transfer.

Published in:

2007 Proceedings 57th Electronic Components and Technology Conference

Date of Conference:

May 29 2007-June 1 2007