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In this work, a methodology for the co-simulation of integrated circuit (IC), package, and printed circuit board (PCB) for low-power applications is presented. First, it is shown through numerical experiments that system-level characterization achieved by considering the chip, package, and board as autonomous blocks that interact with each other via simplistic schematic-level connections is insufficient to capture critical details. With that established, physical extraction based on an unstructured triangulization of the power delivery network (PDN) metalization that can readily adapt to the multiple length scales encountered in a single, integrated chip-package-board (CPB) physical model is proposed and validated against measurements. Finally, CPB system response is evoked with a macromodel of the core power delivery network driving the physical CPB model. Observed time-domain signatures match numerical predictions reasonably well.