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Embedded Chip Build-Up Using Fine Line Interconnect

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4 Author(s)
Ray Fillion ; General Electric, 1 Research Circle, Niskayuna, NY 12309. 518-387-6199, ; Charles Woychik ; Tan Zhang ; Don Bitting

Advanced packaging technologies are driven by two generally balanced forces: performance advances being made by the semiconductor industry and the product requirements of the leading electronics markets. The semiconductor advancements include shrinking feature sizes and innovative transistor structures that provide ever more functionality per unit area of silicon and faster clock rates. One of the leading electronics markets is the portable electronics market, covering cell phones, digital assistants, portable entertainment and digital cameras. These products are driving smaller and thinner packages, finer featured substrates, multichip packages, such as SiPs (System-in-Packages) and 3-D stacking. They are also driving to mixed analog, digital, and RF circuitry within one package with increasing concerns with interconnect parasitics, EMI shielding and thermal performance. A new family of embedded chip packaging and interconnection approaches are being developed to address the next generation portable electronics circuits. These embedded chip approaches feature embedded actives and passives, micro-vias, thin film polymer dielectrics and fine line build-up interconnections. This paper will look at a number of embedded chip approaches including the GE Embedded Chip Build-Up technology and analyze the electrical, density, reliability and cost advantages of this approach and show examples of its use in chip scale, chip carrier, and SiP applications for portable electronics applications.

Published in:

2007 Proceedings 57th Electronic Components and Technology Conference

Date of Conference:

May 29 2007-June 1 2007