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As chip I/O count continues to increase, the C4 bump pitch needs to be further reduced. In this work, a Si-based test carrier was used for characterization of ultra-fine pitch micro C4s. Successful assembly and rework of die with 11,892 micro C4s were demonstrated. The micro C4 contact resistance was measured for various pad geometries. The mechanical shear force was characterized for several variables including contact pad area, pad shape, and shear direction. When joined onto pads with reduced size, the micro C4s were sheared without significant damage. Therefore, a carrier with reduced-size bonding pads can be utilized as a platform for functional test and burn-in followed by chip removal to create know-good-die (KGD). These high I/O KGD can be joined to a multi-chip module, silicon package or stacked to create chip stacks and tested to create known-good-modules (KGM) or known-good-die-stacks (KGDS). This specialized high I/O silicon carrier with full area array, reduced-area bonding pads is also referred to as a temporary chip attachment (TCA) substrate.