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A thin flip-chip (FC) BGA with a 65 nm device has been developed for the bottom package of package on package (PoP) packaging for mobile equipment. The device has a low-k interlayer dielectric (ILD) that is known to be fragile material, and the device and the substrate are connected by lead-free solder bumps in taking environmental safeguards into account. The bumps are arranged in 120 um pitch staggered array. A package height of as low as 0.85 mm (nom) was established and 0.76 mm (nom) is under development. To use this package of 0.76 mm (nom) heights for PoP packaging the total height of the PoP after stacking a memory MCP with a height of 0.85 mm (nom) result in a total height of 1.4 mm (max). The package size is 14 mm sq., and we are able to produce larger package size applying the developed techniques. This paper explains three challenges in developing a thin FCBGA. The challenges are, first, the warpage of a thin package, second, connective reliabilities of solder bumps, and last, reliabilities of the 65 nm device with low-k ILD. The influence of making package thinner was examined by the stress simulation using various die and substrate thicknesses. And the verification experiment was also conducted. Then, the further simulation was conducted to reduce the package warpage, which is significant to the thinner outline, and to examine the stresses derived from reduced warpage, using various package materials. The package warpage of 80um or less was the result of the simulation for the optimum combination of the materials, and was confirmed by the physical experiments. This package also passed the qualification test. Thus, a thin FCBGA that has high reliability and low warpage was developed.