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Low-temperature f.e.t. for low-power high-speed logic

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3 Author(s)
Rees, H. ; RSRE, Malvern, UK ; Sanghera, G.S. ; Warriner, R.A.

A novel f.e.t. cooled to around 100 K is proposed. Detailed computer simulations support the conjecture of high-speed switching at low power levels with a power-delay product ¿ 10¿14 J.

Published in:

Electronics Letters  (Volume:13 ,  Issue: 6 )